Comments on: Moore’s law http://blog.elisehuard.be/2007/12/moores-law/ Thu, 04 Aug 2011 20:01:41 +0000 hourly 1 http://wordpress.org/?v= By: Ray http://blog.elisehuard.be/2007/12/moores-law/comment-page-1/#comment-4828 Ray Fri, 06 May 2011 10:47:54 +0000 http://blog.elisehuard.be/?p=263#comment-4828 http://newsroom.intel.com/community/intel_newsroom/blog/2011/05/04/intel-reinvents-transistors-using-new-3-d-structure http://newsroom.intel.com/community/intel_newsroom/blog/2011/05/04/intel-reinvents-transistors-using-new-3-d-structure

]]> By: elise http://blog.elisehuard.be/2007/12/moores-law/comment-page-1/#comment-591 elise Sun, 16 Dec 2007 18:37:47 +0000 http://blog.elisehuard.be/?p=263#comment-591 @pixel: yes, graphical application seem very parallelizable to me. @peter : very interesting ! you're much more of an expert than i am. A new, more complex law is indeed called for @pixel: yes, graphical application seem very parallelizable to me.
@peter : very interesting ! you’re much more of an expert than i am. A new, more complex law is indeed called for

]]> By: PeterV http://blog.elisehuard.be/2007/12/moores-law/comment-page-1/#comment-590 PeterV Sun, 16 Dec 2007 18:20:41 +0000 http://blog.elisehuard.be/?p=263#comment-590 I believe one very important aspect needs to be added to the equation and that is <em>power</em> (electrical power). Both for the limit of how much heat can be extracted from the chip in high-end computing and how much battery power can be consumed for low-power/portable computing, the real challenge is MIPS/Watt (or reverse Joule/instruction). The Moore law was about Si (silicon) area being the limiting factor. Let's say a 20*20 mm2 chip is the maximum practical size for a chip, the Moore's law dictates how much transistors can go on a chip and at how much GHz they can run. But the real challenge now is MIPS/Watt (and not longer MIPS/mm2). And the core trick is that <em>lower frequencies</em> are more efficient in MIPS/Watt (because it allows you to further lower the voltage of the chip, which to the 2nd power reduces the energy consumed by each flip of a bit (E = C.V2/2)). The most extreme example I remember up to now is the cochlear hearing implant of Cochlear.be (developed in Mechelen), that uses 16 parallel dedicated processors at 5 MHz (yes, 0.005 GHz) to do all audio processing for a power of a few microWatts (so the entire processor can run for a day on a very small charge that is applied with an electromagnetic coil to the electronics implanted inside the body of the patient). I wrote something (in Dutch) earlier about the questions of <a href="http://www.vandenabeele.com/Erlang-parallel-processing" rel="nofollow">languages optimal for parallel processing</a>. I believe one very important aspect needs to be added to the equation and that is power (electrical power). Both for the limit of how much heat can be extracted from the chip in high-end computing and how much battery power can be consumed for low-power/portable computing, the real challenge is MIPS/Watt (or reverse Joule/instruction). The Moore law was about Si (silicon) area being the limiting factor. Let’s say a 20*20 mm2 chip is the maximum practical size for a chip, the Moore’s law dictates how much transistors can go on a chip and at how much GHz they can run. But the real challenge now is MIPS/Watt (and not longer MIPS/mm2). And the core trick is that lower frequencies are more efficient in MIPS/Watt (because it allows you to further lower the voltage of the chip, which to the 2nd power reduces the energy consumed by each flip of a bit (E = C.V2/2)). The most extreme example I remember up to now is the cochlear hearing implant of Cochlear.be (developed in Mechelen), that uses 16 parallel dedicated processors at 5 MHz (yes, 0.005 GHz) to do all audio processing for a power of a few microWatts (so the entire processor can run for a day on a very small charge that is applied with an electromagnetic coil to the electronics implanted inside the body of the patient). I wrote something (in Dutch) earlier about the questions of languages optimal for parallel processing.

]]> By: pixel http://blog.elisehuard.be/2007/12/moores-law/comment-page-1/#comment-589 pixel Sun, 16 Dec 2007 18:19:18 +0000 http://blog.elisehuard.be/?p=263#comment-589 Very intresting article. Do you know the Blinn's law (from the name of the bump mapping inventor) often used in CG industry : It states that regardless of hardware, all renderings take about the same amount of time. Because more power you have, more effects you add. And in these applications, parallelization is not a real issue (rendering farm were already built on a multi CPU basis before multi cores) So, things are not going to change, rendering won't take less time in the future ;) Very intresting article. Do you know the Blinn’s law (from the name of the bump mapping inventor) often used in CG industry : It states that regardless of hardware, all renderings take about the same amount of time. Because more power you have, more effects you add.

And in these applications, parallelization is not a real issue (rendering farm were already built on a multi CPU basis before multi cores)

So, things are not going to change, rendering won’t take less time in the future ;)

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